View IDT74FCT162701AT_281377.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 18-BIT READ/WRITE BUFFER
IDT74FCT162701T/AT
FEATURES:
* * * * * * * * * * * * *
0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1A (max.) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Balanced Output Drivers (24mA) Reduced system switching noise Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25C Ideal for new generation x86 write-back cache solutions Suitable for modular x86 architectures Four deep write FIFO Latch in read path Synchronous FIFO reset Available in SSOP and TSSOP packages
DESCRIPTION:
The FCT162701T is an 18-bit Read/Write buffer with a four deep FIFO and a read-back latch. It can be used as a read/write buffer between a CPU and memory or to interface a high-speed bus and a slow peripheral. The A-to-B (write) path has a four deep FIFO for pipelined operations. The FIFO can be reset and a FIFO full condition is indicated by the full flag (FF). The B-to-A (read) path has a latch. A high on LE, allows data to flow transparently from B-to-A. A low on LE allows the data to be latched on the falling edge of LE. The FCT162701T has a balanced output drive with series termination. This provides low ground bounce, minimal undershoot and controlled output edge rates.
FUNCTIONAL BLOCK DIAGRAM
A1-18
18
OEBA
RESE T CLK W CE RCE FF FIFO (4 deep) LATCH LE
OEA B
18
B1-18
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c) 2002 Integrated Device Technology, Inc.
JANUARY 2002
DSC-2915/1
IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEA B W CE A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEB A LE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RCE CLK B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 FF RESET
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(3) TSTG IOUT Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to 7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA VTERM(2) Terminal Voltage with Respect to GND
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals for FCT162XXX.
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
SSOP/ TSSOP TOP VIEW
PIN DESCRIPTION
Pin Names A1-18 B1-18 CLK I/O I/O I/O I 18 bit I/O port 18 bit I/O port Clock for write path FIFO. Clocks data into FIFO when WCE is low, clocks data out of FIFO when RCE is low. When FIFO is full all further writes to the FIFO are inhibited. When FIFO is empty all reads from the FIFO are inhibited. CLK also resets the FIFO when RESET is low. Enable pin for FIFO input clock Enable pin for FIFO output clock Write path FIFO full flag. Goes low when FIFO is full. Synchronous FIFO reset - when low CLK resets the FIFO. The FIFO pointers are initialized to the "empty" condition and FIFO output is forced high (all ones). The FIFO full flag (FF) will be high immediately after reset. Output Enable pin for B port Output Enable pin for A port Read path latch enable pin. When high, data flows transparently from B port to A port, B data is latched on the falling edge of LE. Description
WCE RCE FF RESET OEAB OEBA LE
I I O I I I I
2
IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
This device is useful as a read/write buffer for modular high end designs. It provides multi-level buffering in the write path and single deep buffering in the read path, and is suited to write back cache implementation. The read path provides a transparent latch. The four deep FIFO uses one clock with two clock enable pins, WCE and RCE to clock data in and out. The FIFO has an external full flag which goes LOW when the FIFO is full. Internal read and write pointers keep track of the words stored in the FIFO. A write attempt to a full FIFO is ignored. An attempt to read from an empty FIFO will have no effect and the last read data remains at the output of the FIFO. The FIFO may be reset by the synchronous RESET
input. This resets the read and write pointers to the original "empty" condition and also sets all B outputs = 1. Simultaneous read and write attempts (clock data into FIFO as well as clock data out of FIFO) are possible except on FIFO empty and full boundaries. When the FIFO is empty, and a simultaneous read and write is attempted, the read is ignored while the write is executed. If the same is attempted when the FIFO is full, the write is ignored while the read is executed. Normal operation of the four deep FIFO in the write path is independent of the read path operation. Power, ground and data pin positions on the FCT162701T match those on the FCT16501T/162501T, allowing an easy upgrade.
APPLICATIONS--486 INTERFACE
CacheRAM
Coprocessor
i486 FCT162701T A B
DRAM
W /R
CLK CLK,W CE, RCE, RST PAL LE,OEBA, OEAB
Figure 1. FCT162701T Application Example
3
IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 10%
Symbol VIH VIL IIH Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins) Input HIGH Current (I/O pins) IIL
(4) (4) (4)
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC
Min. 2 -- -- --
Typ.(2) -- -- -- -- -- -- -- -- -0.7 -140 100 5
Max. -- 0.8 1 1 1 1 1 1 -1.2 -250 -- 500
Unit V V A
Input LOW Current (Input pins) Input LOW Current (I/O pins)
VI = GND
-- --
(4)
IOZH IOZL VIK IOS VH ICCL ICCH ICCZ
High Impedance Output Current (3-State Output pins)
(4)
VCC = Max.
VO = 2.7V VO = 0.5V
-- -- -- -80
A
Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current
VCC = Min., IIN = -18mA VCC = Max., VO = GND(3) -- VCC = Max. VIN = GND or VCC
V mA mV A
-- --
OUTPUT DRIVE CHARACTERISTICS
Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) Min. 60 -60 2.4 -- Typ.(2) 115 -115 3.3 0.3 Max. 200 -200 -- 0.55 Unit mA mA V V
VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOL = 24mA IOH = -24mA
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. The test limit of this parameter is 5A at TA = -55C.
4
IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD (CLK) ICCD (O/P) IC Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current due to clock switching(4) Dynamic Power Supply Current due to clock switching(4) Total Power Supply Current(6) VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OEAB = GND; OEBA = VCC LE = WCE = RCE = GND RESET = VCC All Inputs Low VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OEAB = GND; OEBA = VCC LE = WCE = RCE = GND RESET = VCC One Bit Toggling at fO = 5MHz 50% Duty Cycle
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (CLK) x fCP + ICCD (O/P) x fO NO ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at D ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fO = Output Frequency NO = Number of Outputs at fO
Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open CLK Toggling 50% Duty Cycling One Input Toggling 50% Duty Cycle VIN = VCC VIN = GND VIN = VCC VIN = GND
Min. -- -- -- --
Typ.(2) 0.5 180 80 1.8
Max. 1.5 240 120 2.9(5)
Unit A A/ MHz
mA
VIN = 3.4V VIN = GND
--
2.1
3.7(5)
VIN = VCC VIN = GND
--
2.2
3.5
VIN = 3.4V VIN = GND
--
2.7
5
5
IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162701T Parameter PROPAGATION DELAYS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 B1-18 to A1-18 LE (LOW to HIGH) to A1-18 CLK to FF CLK to B1-18 A1-18 to CLK (LOW to HIGH) Setup A1-18 to CLK (LOW to HIGH) Hold B1-18 to LE (HIGH to LOW) Setup B1-18 to LE (HIGH to LOW) Hold WCE, RCE (LOW) to CLK Setup WCE, RCE (LOW) to CLK Hold RESET (LOW) to CLK Setup RESET (LOW) to CLK Hold OEBA LOW to A1-18 Enable OEBA HIGH to A1-18 Disable OEAB LOW to B1-18 Enable OEAB HIGH to B1-18 Disable CLK HIGH or LOW Pulse Width LE HIGH Pulse Width Read path/latch Read path/latch Write path Write path Write path Write path Read path/latch Read path/latch Write path Write path Write path Write path Write path Write path Read path Read path Write path Read path/latch 1.5 1.5 2 1 2.5 0 3 0 3 0 3 0 1.5 1.5 1.5 1.5 3 3 6.5 5.7 7 6 -- -- -- -- -- -- -- -- 7 6 7 6 -- -- 1.5 1.5 2 1 2.5 0 3 0 3 0 3 0 1.5 1.5 1.5 1.5 3 3 5.5 4.7 6 5.2 -- -- -- -- -- -- -- -- 6 5 6 5 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions(1) Min.(2) Max.(2) FCT162701AT Min.(2) Max.(2) Unit
SETUP & HOLD TIMES(3)
ENABLE & DISABLE TIMES(3)
MINIMUM PULSE WIDTHS
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Guaranteed but not tested.
6
IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 7.0V 500 V IN Pulse Generator D.U.T. 50pF RT 500 CL V OUT
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
DATA INPUT tSU TIMING INPUT ASYNCHR ONOUS C ONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE
1.5V
1.5V
tSU
Pulse Width
tH
Set-up, Hold, and Release Times
ENABLE SAM E PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
DISABLE 3V
CONTROL INPUT tPZL OUTPUT NORMALLY LOW SW ITCH CLOSED tPZH OUTPUT NORMALLY HIGH SW ITCH OPEN 3.5V 1.5V 0.3V tPHZ 0.3V 1.5V 0V tPLZ
1.5V 0V 3.5V VOL VOH
Propagation Delay
0V
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
7
IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX Temp. Range FCT XXX Family XXXX Device Type XX Package
PV PA
Shrink Small Outline Package Thin Shrink Small Outline Package
701T 701AT
18-Bit Read/W rite Buffer
162
Double-Density, 5 Volt, Balanced Drive
74
- 40C to +85C
DATA SHEET DOCUMENT HISTORY 1/21/2002 Removed Military temp grade
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
8

▲Up To Search▲

Price & Availability of IDT74FCT162701AT

	To Download IDT74FCT162701AT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .